As part of its Developer Forum keynote, Intel today showed the first working example of chips built on a 22 nanometer (nm) process. The process is even smaller than the 32nm technology just entering production and should run even more efficiently while fitting more into a given space. A single example chip about the size of a fingernail contains about 2.9 billion transistors and about 364 megabits (45.5MB) of static RAM.
The semiconductor firm didn't say when full 22nm processors would ship, though the company normally employs a "tick, tock" schedule where it introduces a smaller manufacturing process (the "tick") and then a new architecture to exploit that process (the "tock"); 32nm is only due to enter full scale production late this year and makes 22nm more likely for 2011.
Simultaneously, the company also reiterated its plans for Sandy Bridge, the architecture that will take advantage of the nearer 32nm process. It will integrate a new graphics core into the chip die itself, improving the performance of integrated video significantly compared to the existing Nehalem's separate graphics. These designs should also incorporate Advanced Vector Extensions, a new set of extensible instructions that can handle 256-bit data (versus 128-bit for SSE4) and process four tasks at once.
Previous roadmap leaks have also suggested that Sandy Bridge will allow for as many as eight cores in a single processor and 16MB of Level 3 cache on each chip.
The semiconductor firm didn't say when full 22nm processors would ship, though the company normally employs a "tick, tock" schedule where it introduces a smaller manufacturing process (the "tick") and then a new architecture to exploit that process (the "tock"); 32nm is only due to enter full scale production late this year and makes 22nm more likely for 2011.
Simultaneously, the company also reiterated its plans for Sandy Bridge, the architecture that will take advantage of the nearer 32nm process. It will integrate a new graphics core into the chip die itself, improving the performance of integrated video significantly compared to the existing Nehalem's separate graphics. These designs should also incorporate Advanced Vector Extensions, a new set of extensible instructions that can handle 256-bit data (versus 128-bit for SSE4) and process four tasks at once.
Previous roadmap leaks have also suggested that Sandy Bridge will allow for as many as eight cores in a single processor and 16MB of Level 3 cache on each chip.
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